PLL702-01

Clock Generator for PowerPC Based Applications

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991

www.phaselink.com

Rev 07/18/05 Page 4

APPLICATION DIAGRAM: BI-DIRECTIONAL PINS WITH INTERNAL PULL-UP

Latch

Power Up

Reset

Jumper options

R

Clock Load

Latched

Input

Output

EN

VDD

R

up

Bi-directional pin

R

RB

NOTE: Rup=Internal pull-up resistor (see pin description). Power-up Reset : R starts from 1 to 0 while RB starts from 0 to 1.

Internal to chip

External Circuitry