HCS08 datasheet(92/374 Pages) NXP

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Chapter 6 Parallel Input/Output

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

6.5.9

Port E I/O Registers (PTED and PTEDD)

Port E parallel I/O function is controlled by the registers listed below.

6.5.10

Port E Pin Control Registers (PTEPE, PTESE, PTEDS)

In addition to the I/O control, port E pins are controlled by the registers listed below.

321

PTED7

PTED6

PTED5

PTED4

PTED3

PTED2

PTED1

PTED0

Reset

000

Figure 6-22. Port E Data Register (PTED)

Table 6-21. PTED Register Field Descriptions

Field

Description

7:0

PTED[7:0]

Port E Data Register Bits — For port E pins that are inputs, reads return the logic level on the pin. For port E

pins that are configured as outputs, reads return the last value written to this register.

Writes are latched into all bits of this register. For port E pins that are configured as outputs, the logic level is

driven out the corresponding MCU pin.

Reset forces PTED to all 0s, but these 0s are not driven out the corresponding pins because reset also configures

all port pins as high-impedance inputs with pullups disabled.

321

PTEDD7

PTEDD6

PTEDD5

PTEDD4

PTEDD3

PTEDD2

PTEDD1

PTEDD0

Reset

000

Figure 6-23. Data Direction for Port E (PTEDD)

Table 6-22. PTEDD Register Field Descriptions

Field

Description

7:0

PTEDD[7:0]

Data Direction for Port E Bits — These read/write bits control the direction of port E pins and what is read for

PTED reads.

0 Input (output driver disabled) and reads return the pin value.

1 Output driver enabled for port E bit n and PTED reads return the contents of PTEDn.

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