HCS08 datasheet(31/374 Pages) NXP

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Chapter 2 Pins and Connections

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

2.3.3

RESET Pin

RESET is a dedicated pin with a pullup device built in. It has input hysteresis, a high current output driver,

and no output slew rate control. Internal power-on reset and low-voltage reset circuitry typically make

external reset circuitry unnecessary. This pin is normally connected to the standard 6-pin background

debug connector, so a development system can directly reset the MCU system. If desired, a manual

external reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset).

Whenever any reset is initiated (whether from an external source or from an internal source, the RESET

pin is driven low for approximately 66 bus cycles and released. The reset circuity decodes the cause of

reset and records it by setting a corresponding bit in the system control reset status register (SRS).

In EMC-sensitive applications, an external RC filter is recommended on the reset pin. See Figure 2-4 for

an example.

2.3.4

Background/Mode Select (BKGD/MS)

When in reset, the BKGD/MS pin functions as a mode select pin. Immediately after reset rises the pin

functions as the background pin and can be used for background debug communication. While functioning

as a background/mode select pin, the pin includes an internal pullup device, input hysteresis, a standard

output driver, and no output slew rate control.

If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset.

If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low

during the rising edge of reset which forces the MCU to active background mode.

The BKGD pin is used primarily for background debug controller (BDC) communications using a custom

protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC

clock could be as fast as the bus clock rate, so there must never be any significant capacitance connected

to the BKGD/MS pin that could interfere with background serial communications.

Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol

provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from

cables and the absolute value of the internal pullup device play almost no role in determining rise and fall

times on the BKGD pin.

2.3.5

ADC Reference Pins (VREFH, VREFL)

The VREFH and VREFL pins are the voltage reference high and voltage reference low inputs respectively

for the ADC module.

2.3.6

External Interrupt Pin (IRQ)

The IRQ pin is the input source for the IRQ interrupt and is also the input for the BIH and BIL instructions.

If the IRQ function is not enabled, this pin can be used for TPMCLK.

In EMC-sensitive applications, an external RC filter is recommended on the IRQ pin. See Figure 2-4 for

an example.

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