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K32L2AX Folha de dados(PDF) 76 Page - NXP Semiconductors |
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K32L2AX Folha de dados(HTML) 76 Page - NXP Semiconductors |
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76 / 96 page ![]() EMVSIMn_VCCEN EMVSIMn_CLK EMVSIMn_IO 2 T0 1 RESPONSE EMVSIMn_RST T1 3 3 Figure 20. Active-Low-Reset Smart Card Reset Sequence The following table defines the general timing requirements for the EMVSIM interface.. Table 45. Timing Specifications, Internal Reset Card Reset Sequence Ref No Min Max Units 1 — 200 EMVSIMx_CLK clock cycles 2 400 40,000 EMVSIMx_CLK clock cycles 3 40,000 — EMVSIMx_CLK clock cycles 8.8.1.2 EMVSIM Power-Down Sequence Following figure shows the EMV SIM interface power-down AC timing diagram.Table 46 table shows the timing requirements for parameters (SI7–SI10) shown in the figure. The power-down sequence for the EMV SIM interface is as follows: • EMVSIMn_SIMPD port detects the removal of the Smart Card • EMVSIMn_RST is negated • EMVSIMn_CLK is negated • EMVSIM_IO is negated • EMVSIMx_VCCENy is negated Each of the above steps requires one OSC32KCLK period (usually 32 kHz, also known as rtcclk in below figure). Power-down may be initiated by a Smart card removal detection; or it may be launched by the processor. Peripheral operating requirements and behaviors 76 K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021 NXP Semiconductors |
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