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IMXRT1010IEC Folha de dados(PDF) 6 Page - NXP Semiconductors |
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IMXRT1010IEC Folha de dados(HTML) 6 Page - NXP Semiconductors |
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6 / 65 page ![]() i.MX RT1010 Crossover Processors Data Sheet for Industrial Products, Rev. 0, 09/2019 6 NXP Semiconductors Architectural overview 2 Architectural overview The following subsections provide an architectural overview of the i.MX RT1010 processor system. 2.1 Block diagram Figure 2 shows the functional modules in the i.MX RT1010 processor system1. . Figure 2. i.MX RT1010 system block diagram 1. Some modules shown in this block diagram are not offered on all derivatives. See Table 1 for details. Power Management External Memory Connectivity 4 x 4 Keypad Security I2C x2 UART x4 GPIO SPI x2 Internal Memory System Control Security JTAG PLL / OSC RTC and Reset Embedded DMA IOMUX GP Timer x3 CPU Platform ARM Cortex-M7 16 KB I-cache 8 KB D-cache FPU Dual-Channel Quad-SPI Octal/Hyper Flash/RAM FlexSPI with on-the-fly AES decryption MPU NVIC 128K I-TCM and D-TCM 64 KB ROM HAB FlexPWM x1 Watch Dog x4 DCDC LDO I2S / SAI x2 Ciphers RNG SPDIF Tx/Rx HSGPIO MQS USB2.0 OTG with PHY x1 128 KB SRAM shared with TCM FlexIO Secure RTC eFuse Temp Monitor ADC ADC (15-ch) x1 |
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