IMXRT1010IEC datasheet(21/65 Pages) NXP

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Electrical characteristics

i.MX RT1010 Crossover Processors Data Sheet for Industrial Products, Rev. 0, 09/2019

NXP Semiconductors

NOTE

The currents on the VDD_HIGH_CAP and VDD_USB_CAP were

identified to be the voltage divider circuits in the USB-specific level

shifters.

4.2

System power and clocks

This section provide the information about the system power and clocks.

4.2.1

Power supplies requirements and restrictions

The system design must comply with power-up sequence, power-down sequence, and steady state

guidelines as described in this section to guarantee the reliable operation of the device. Any deviation

from these sequences may result in the following situations:

•

Excessive current during power-up phase

•

Prevention of the device from booting

•

Irreversible damage to the processor (worst-case scenario)

Figure 3. Power sequence

4.2.1.1

Power-up sequence

The below restrictions must be followed:

•

VDD_SNVS_IN supply must be turned on before any other power supply or be connected

(shorted) with VDD_HIGH_IN supply.

•

If a coin cell is used to power VDD_SNVS_IN, then ensure that it is connected before any other

supply is switched on.

•

When internal DCDC is enabled, external delay circuit is required to delay the

“DCDC_PSWITCH” signal at least 1 ms after DCDC_IN is stable.

•

POR_B should be held low during the entire power up sequence.

Run Mode <-> SNVS Mode

Run Mode <-> Standby Mode

Power On

VDD_SNVS_IN

DCDC_IN

POR_B

PMIC_ON_REQ

ON_OFF

VDD_SOC_IN

DCDC_OK

DCDC_PSWITCH

VDD_HIGH_CAP

NVCC_PLL

VDD_SNVS_CAP

PMIC_STBY_REQ

TStbyExt

TSNVSDly

TDCDCSetup

1ms

Signal in VDD_SOC power

domain

Signal in DCDC_IN power

domain

Signal in VDD_SNVS_CAP

power domain

VDD_SOC power rail

DCDC_IN power rail

VDD_SNVS_CAP power rail

VDDA_2P5_CAP power rail

VDDA_1P1_CAP power rail

VDD_SNVS_IN power rail

DCDC_LP power rail

LEGEND

Signal Floating

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