5.3

Rail-to-rail input stage

The TSB711, TSB711A, TSB712, TSB712A devices are built with two complementary NPN and PNP input

differential pairs, as shown in the figure below.

GND

[ … ]

[ … ]

[ … ]

[ … ]

In

Ip

Nn

Np

VIN

VIP

Pn

Pp

V. However, the performance of these devices is optimized for the P-channel differential pair (which means

transition occurs between the P-channel and the N-channel differential pair, impacting the input offset voltage (see

Figure 12. Input offset voltage vs. common mode voltage at VCC = 5 V TSB711A, TSB712A and Figure 13. Input

offset voltage vs. common mode voltage at VCC = 36 V TSB711A, TSB712A). As a consequence, CMRR can

be degraded around this transition region. In order to achieve the best possible performance, this operating point

should be avoided.

Please also notice that the input bias current polarity depends on the operation of NPN or PNP input stage.

This transition is visible in figures Figure 16. Input bias current vs. common mode voltage at VCC = 5 V and

Figure 17. Input bias current vs. common mode voltage at VCC = 36 V.

5.4

Input offset voltage drift over the temperature

The maximum input voltage drift variation over temperature is defined as the offset variation related to the offset

value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain,

and the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C

can be compensated during the production at application level. The maximum input voltage drift overtemperature

enables the system designer to anticipate the effect of temperature variations. The maximum input voltage drift

overtemperature is computed using the following formula:

ΔVioΔT=maxVioT−Vio25°C

T−25°C T=−40°CandT=125°C

(1)

The datasheet maximum value is guaranteed by a measurement on a representative sample size ensuring a Cpk

(process capability index) greater than 1.3.

TSB711, TSB711A, TSB712, TSB712A, TSB714, TSB714A

Rail-to-rail input stage

DS12487 - Rev 6

page 18/36