UCD3138064RMHT datasheet(74/104 Pages) TI

Nome de Peças	UCD3138064RMHT

Descrição Electrónicos	UCD3138064 Highly Integrated Digital Controller for Isolated Power With 64-kB Program Flash Memory

PDF	104 Pages

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Fabricante Electrônico	TI [Texas Instruments]

Página de início	http://www.ti.com

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a chip reset. To prevent POR trigger signal oscillation and successive chip resets, TI recommends a minimum

slew rate of 2.6 V/ms.

VDROOP

V3P3

POR (internal)

tPOR

V33 (Volts)

3.6

3.3

3.0 (Vtarget)

VGH

Figure 11-1. V33 Voltage Dip When POR is Activated

From the V33 Voltage Dip When POR is Activated recommendations, the slew rate using the 2.2 uF/1uF

capacitor combination requires that the slew rate must be as follows:

6 V / ms

2.6 V / ms

(1)

11.4 Recommendation for RC Time Constant of RESET Pin for UCD3138 and UCD3138064

Ideally, the ARM core should begin execution of ROM code only after V33>3V. The ROM code reads trim

values and loads trim registers. Lack of sufficient voltage during this operation can result in unexpected device

functioning. Depending on V33 slew rate, the duration for which there is insufficient voltage on V33 is varied.

During this time, a reliable trim operation is not ensured. Applying an RC filter between V33 and the RESET pin

can increase the delay from V33 power up to the device coming out of reset.

UCD3138064

SLUSB72D – MARCH 2013 – REVISED APRIL 2021

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