LSM6DSR datasheet(72/168 Pages) STMICROELECTRONICS

72 / 168 page

9.41

FIFO_STATUS1 (3Ah)

FIFO status register 1 (r)

Table 114. FIFO_STATUS1 register

DIFF_FIFO_7 DIFF_FIFO_6 DIFF_FIFO_5 DIFF_FIFO_4 DIFF_FIFO_3 DIFF_FIFO_2 DIFF_FIFO_1 DIFF_FIFO_0

Table 115. FIFO_STATUS1 register description

DIFF_FIFO_[7:0]

Number of unread sensor data (TAG + 6 bytes) stored in FIFO

In conjunction with DIFF_FIFO[9:8] in FIFO_STATUS2 (3Bh).

9.42

FIFO_STATUS2 (3Bh)

FIFO status register 2 (r)

Table 116. FIFO_STATUS2 register

FIFO_

WTM_IA

FIFO_

OVR_IA

FIFO_

FULL_IA

COUNTER_

BDR_IA

FIFO_OVR_

LATCHED

DIFF_FIFO_9 DIFF_FIFO_8

Table 117. FIFO_STATUS2 register description

FIFO_WTM_IA

FIFO watermark status. Default value: 0

(0: FIFO filling is lower than WTM;

1: FIFO filling is equal to or greater than WTM)

Watermark is set through bits WTM[8:0] in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h).

FIFO_OVR_IA

FIFO overrun status. Default value: 0

(0: FIFO is not completely filled; 1: FIFO is completely filled)

FIFO_FULL_IA

Smart FIFO full status. Default value: 0

(0: FIFO is not full; 1: FIFO will be full at the next ODR)

COUNTER_BDR_IA

Counter BDR reaches the CNT_BDR_TH_[10:0] threshold set in COUNTER_BDR_REG1 (0Bh) and

COUNTER_BDR_REG2 (0Ch). Default value: 0

This bit is reset when these registers are read.

FIFO_OVR_LATCHED

Latched FIFO overrun status. Default value: 0

This bit is reset when this register is read.

DIFF_FIFO_[9:8]

Number of unread sensor data (TAG + 6 bytes) stored in FIFO. Default value: 00

In conjunction with DIFF_FIFO[7:0] in FIFO_STATUS1 (3Ah).

LSM6DSR

FIFO_STATUS1 (3Ah)

DS11976 - Rev 2

page 72/168

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