JS28F256P30T85 datasheet(82/102 Pages) INTEL

82 / 102 page

1-Gbit P30 Family

April 2005

Intel StrataFlash® Embedded Memory (P30)

Datasheet

Order Number: 306666, Revision: 001

Figure 38.

Write State Machine—Next State Table (Sheet 5 of 6)

Read

Array

(2)

Word

Program

Setup (3,4)

BP Setup

Erase

Setup

(3,4)

Buffered

Enhanced

Factory Pgm

Setup

(3, 4)

BE Confirm,

P/E

Resume,

ULB Confirm

(8)

Program/

Erase

Suspend

Read

Status

Clear

Status

(5)

Read

ID/Query

Lock, Unlock,

Lock-down,

CR setup

(4)

(FFH)

(10H/40H)

(E8H)

(20H)

(30H)

(D0H)

(B0H)

(70H)

(50H)

(90H, 98H)

(60H)

Status Read

Command Input to Chip and resulting Output Mux Next State

Output Next State Table

Status Read

Output mux

does not

change.

Status

Read

ID Read

Status Read

Ready,

Erase Suspend,

BP Suspend

Status Read

Lock/CR Setup,

Lock/CR Setup in

Erase Susp

Output does not change.

Status Read

BEFP Setup,

BEFP Pgm & Verify

Busy,

Erase Setup,

OTP Setup,

BP: Setup, Load 1,

Load 2, Confirm,

Word Pgm Setup,

Word Pgm Setup in

Erase Susp,

BP Setup, Load1,

Load 2, Confirm in

Erase Suspend

Current chip state

OTP Busy

BP Busy,

Word Program

Busy,

Erase Busy,

BP Busy

BP Busy in Erase

Suspend

Word Pgm

Suspend,

Word Pgm Busy in

Erase Suspend,

Pgm Suspend In

Erase Suspend

Read Array

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