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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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AM652X Folha de dados(PDF) 239 Page - Texas Instruments |
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AM652X Folha de dados(HTML) 239 Page - Texas Instruments |
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239 / 277 page  TDO J2 J1 J4 TCK J5 TDI / TMS J3 J6 J7 J4 J5 TRC_DATA TRC_CLK ( ) ( ) Worst Case 1 (Ideal) Worst Case 2 DBTR1 DBTR2 DBTR3 DBTR4 DBTR6 DBTR5 DBTR7 DBTR4 DBTR6 DBTR9 DBTR5 DBTR7 DBTR8 DBTR8 DBTR9 SPRSP08_Debug_01 239 AM6548, AM6528, AM6546 AM6526, AM6527 www.ti.com SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019 Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2019, Texas Instruments Incorporated Figure 5-123. Debug Trace Timing 5.9.6.2 IEEE 1149.1 Standard-Test-Access Port (JTAG) For more details about features and additional description information on the device IEEE 1149.1 Standard-Test-Access Port, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. 5.9.6.2.1 JTAG Electrical Data and Timing Table 5-121, Table 5-122, and Figure 5-124 assume testing over the recommended operating conditions and electrical characteristic conditions. Table 5-121. Timing Requirements for IEEE 1149.1 JTAG NO. PARAMETER DESCRIPTION MIN MAX UNIT J1 tc(TCK) Cycle time minimum, TCK 75 ns J2 tw(TCKH) Pulse width minimum, TCK high 30 ns J3 tw(TCKL) Pulse width minimum, TCK low 30 ns J4 tsu(TDI-TCK) Input setup time minimum, TDI valid to TCK high 8 ns tsu(TMS-TCK) Input setup time minimum, TMS valid to TCK high 8 ns J5 th(TCK-TDI) Input hold time minimum, TDI valid from TCK high 5.2 ns th(TCK-TMS) Input hold time minimum, TMS valid from TCK high 5.2 ns Table 5-122. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG NO. PARAMETER DESCRIPTION MIN MAX UNIT J6 td(TCKL-TDOI) Delay time minimum, TCK low to TDO invalid 0 ns J7 td(TCKL-TDOV) Delay time maximum, TCK low to TDO valid 27.75 ns Figure 5-124. JTAG Test-Port Timing |
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