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AM652X Folha de dados(PDF) 236 Page - Texas Instruments |
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AM652X Folha de dados(HTML) 236 Page - Texas Instruments |
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236 / 277 page  PMIT5 MII_TXCLK (input) MII_TXD[3:0], MII_TXEN (outputs) SPRS91x_TIMING_PRU_MII_RT_07 MII_MRCLK (Input) PMIR4 PMIR5 MII_RXD[3:0], MII_RXDV, MII_RXER (Inputs) SPRS91x_TIMING_PRU_MII_RT_06 236 AM6548, AM6528, AM6546 AM6526, AM6527 SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019 www.ti.com Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2019, Texas Instruments Incorporated Table 5-114. PRU_ICSSG MII_RT Timing Requirements – MII_RXD[3:0], MII_RXDV, and MII_RXER (continued) NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PMIR5 th(RX_CLK-RXD) Hold time, RXD[3:0] valid after RX_CLK 10 Mbps 8 ns th(RX_CLK-RX_DV) Hold time, RX_DV valid after RX_CLK 8 ns th(RX_CLK-RX_ER) Hold time, RX_ER valid after RX_CLK 8 ns th(RX_CLK-RXD) Hold time, RXD[3:0] valid after RX_CLK 100 Mbps 8 ns th(RX_CLK-RX_DV) Hold time, RX_DV valid after RX_CLK 8 ns th(RX_CLK-RX_ER) Hold time, RX_ER valid after RX_CLK 8 ns Figure 5-119. PRU_ICSSG MII_RXD[3:0], MII_RXDV, and MII_RXER Timing Table 5-115. PRU_ICSSG MII_RT Switching Characteristics – MII_TXD[3:0] and MII_TXEN NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PMIT5 td(TX_CLK-TXD) Delay time, TX_CLK High to TXD[3:0] valid 10 Mbps 0 25 ns td(TX_CLK-TX_EN) Delay time, TX_CLK to TX_EN valid 0 25 ns td(TX_CLK-TXD) Delay time, TX_CLK High to TXD[3:0] valid 100 Mbps 0 25 ns td(TX_CLK-TX_EN) Delay time, TX_CLK to TX_EN valid 0 25 ns Figure 5-120. PRU_ICSSG MII_TXD[3:0], MII_TXEN Timing For more information, see section Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem - Gigabit (PRU_ICSSG) in the device TRM. 5.9.5.22 Timers For more details about features and additional description information on the device Timers, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. Table 5-116, Table 5-117 and Figure 5-121 present timings and switching characteristics of the Timers. Table 5-116. Timing Requirements for Timers NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT T1 tw(TINPH) Pulse duration, high CAPTURE 5 + 4P(1) ns T2 tw(TINPL) Pulse duration, low CAPTURE 5 + 4P(1) ns |
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