STM32MP153C datasheet(32/254 Pages) STMICROELECTRONICS

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Functional overview

STM32MP153C/F

32/254

DS12503 Rev 3

It is then possible to have two different communication types in each direction.

The IPCC communication data must be located in a common memory, which is not part of

the IPCC block.

3.11.1

IPCC main features

•

Status signaling for the four channels

–

Channel occupied/free flag, also used as lock

•

Two interrupt lines per processor

–

One for RX channel occupied (communication data posted by sending processor)

–

One for TX channel free (communication data retrieved by receiving processor)

•

Interrupt masking per channel

–

Channel occupied mask

–

Channel free mask

•

Two channel operation modes

–

Simplex (each channel has its own communication data memory location)

–

Half duplex (a single channel in associated to a bidirectional communication data

information memory location)

3.12

General-purpose input/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain,

with or without pull-up or pull-down), as input (with or without pull-up or pull-down) or as

peripheral alternate function. Most of the GPIO pins are shared with digital or analog

alternate functions. All GPIOs are high-current-capable and have speed selection to better

manage internal noise, power consumption and electromagnetic emission.

After reset, all GPIOs are in analog mode to reduce power consumption.

The I/O configuration can be locked if needed by following a specific sequence in order to

avoid spurious writing to the I/Os registers.

Additionally, GPIO pins on port Z can be individually set as secure, which would mean that

software accesses to these GPIOs and associated peripherals defined as secure are

restricted to secure software running on Cortex-A7.

3.13

TrustZone protection controller (ETZPC)

ETZPC is used to configure TrustZone security of bus masters and slaves with

programmable-security attributes (securable resources) such as:

•

On-chip SYSRAM with programmable secure region size

•

AHB and APB peripherals to be made secure

Notice that by default, SYSRAM and peripheral are set to secure access only, so, not

accessible by non-secure masters such as Cortex-M4 or DMA1/DMA2.

ETZPC can also allocate peripherals and SRAM to be accessible only by the Cortex-M4

and/or DMA1/DMA2. This ensures the safe execution of the Cortex-M4 firmware, protected

from other masters (e.g. Cortex-A7) unwanted accesses.

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