STM32MP153C datasheet(53/254 Pages) STMICROELECTRONICS

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DS12503 Rev 3

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STM32MP153C/F

Functional overview

Both CAN modules (FDCAN1 and FDCAN2) are compliant with ISO 11898-1 (CAN protocol

specification version 2.0 part A, B) and CAN FD protocol specification version 1.0.

FDCAN1 supports time triggered CAN (TTCAN) specified in ISO 11898-4, including event

synchronized time-triggered communication, global system time, and clock drift

compensation. The FDCAN1 contains additional registers, specific to the time triggered

feature. The CAN FD option can be used together with event-triggered and time-triggered

CAN communication.

A 10 Kbyte message RAM memory implements filters, receive FIFOs, receive buffers,

transmit event FIFOs, transmit buffers (and triggers for TTCAN). This message RAM is

shared between the two FDCAN1 and FDCAN2 modules.

The common clock calibration unit is optional. It can be used to generate a calibrated clock

for both FDCAN1 and FDCAN2 from the HSI internal RC oscillator and the PLL, by

evaluating CAN messages received by the FDCAN1.

3.45

Universal serial bus high-speed host (USBH)

The devices embed one USB high-speed host (up to 480 Mbit/s) with two physical ports.

USBH supports both low, full-speed (OHCI) as well as high-speed (EHCI) operations

independently on each port. It integrates two transceivers which can be used for either low-

speed (1.2 Mbit/s), full-speed (12 Mbit/s) or high-speed operation (480 Mbit/s), the second

high-speed transceiver is shared with OTG high-speed.

The USB HS is compliant with the USB 2.0 specification. The USB HS controllers require

dedicated clocks that are generated by a PLL inside the USB high-speed PHY.

3.46

USB on-the-go high-speed (OTG)

The devices embed one USB OTG high-speed (up to 480 Mbit/s) device/host/OTG

peripheral. OTG supports both full-speed and high-speed operations. It integrates the

transceivers for full-speed operation (12 Mbit/s) and high-speed operation (480 Mbit/s)

shared with USB Host second port.

The USB OTG HS is compliant with the USB 2.0 specification and with the OTG 2.0

specification. It has software-configurable endpoint setting and supports suspend/resume.

The USB OTG controllers require a dedicated 48 MHz clock that is generated by a PLL

inside RCC or inside the USB high-speed PHY.

STM32MP153C Folha de dados(PDF) 53 Page - STMicroelectronics