STM32MP151C datasheet(126/253 Pages) STMICROELECTRONICS

126 / 253 page

Electrical characteristics

STM32MP151C/F

126/253

DS12501 Rev 3

Figure 13. VDDCORE rise time from reset

Table 14. Operating conditions at power-up / power-down

Symbol

Parameter

Min

Max

Unit

tVDD(1)

1. VDD must be present before VDDCORE .

VDD rise time rate

∞

µs/V

VDD fall time rate

∞

tVDDA

VDDA rise time rate

∞

VDDA fall time rate

∞

tVDD3V3_USB(2)

tVDD3V3_USBHS

tVDD3V3_USBFS

2. VDDA1V8_REG must be present before VDD3V3_USBHS.

VDD3V3_USBxx rise time rate

∞

VDD3V3_USBxx fall time rate

∞

tVDDCORE

VDDCORE rise time rate (from

reset to RUN mode)

2000(3)

3. In case VDDCORE rise time is larger than 2 ms/V, user should control the NRST_CORE signal with a Power

Good (PG) control signal from the external regulator to avoid dysfunction of the device due to VDDCORE

potentially not yet established when internal reset signal is de-activated after tVDDCORETEMPO (cf.Table 14

and Figure 13).

VDDCORE rise time rate (from

LPLV-Stop to RUN mode)

1000(4)

4. In case VDDCORE rise time at exit of LPLV-Stop is larger than 1 ms/V, there is a risk of unwanted reset due

to VDDCORE potentially not yet established after tSEL_VDDCORETEMPO (cf.Table 14 and Figure 14). In such a

case, the VDDCORE supply should not be decreased during LPLV-Stop mode.

VDDCORE fall time rate

7.33

∞

MSv47497V2

VDDCORE

pvdcore_out

tVDDCORETEMPO

VDDCORE should be above

VDDCORE Min when vddcore_ok is

enabled

VPVDCORE_0 (rising edge)

vddcore_ok

Run mode

VDDCORE Min = VPVDCORE_0 Min (rising edge) + tVDDCORETEMPO Min / tVDDCORE Max

average rise time rate should be less than

tVDDCORE Max (from reset to Run mode)

VDDCORE Min

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