STM32L4A6RG datasheet(60/282 Pages) STMICROELECTRONICS

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Functional overview

STM32L4A6xG

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DS11584 Rev 8

LCD parallel interface

The FMC can be configured to interface seamlessly with most graphic LCD controllers. It

supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to

specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost

effective graphic applications using LCD modules with embedded controllers or high

performance solutions using external controllers with dedicated acceleration.

For WLCSP100 package, address lines [A18:A16] are missing versus other 100 pin

packages, thus FMC provides only 2MB of addressable space, split into 64K blocks. The

main usage of the FMC in this case is to drive external LCD interface.

3.42

Dual-flash Quad SPI memory interface (QUADSPI)

The Dual-flash Quad SPI is a specialized communication interface targeting single, dual or

quad SPI flash memories. It can operate in any of the three following modes:

•

Indirect mode: all the operations are performed using the QUADSPI registers

•

Status polling mode: the external flash status register is periodically read and an

interrupt can be generated in case of flag setting

•

Memory-mapped mode: the external Flash is memory mapped and is seen by the

system as if it were an internal memory

Both throughput and capacity can be increased two-fold using dual-flash mode, where two

Quad SPI flash memories are accessed simultaneously.

The Dual-flash Quad SPI interface supports:

•

Three functional modes: indirect, status-polling, and memory-mapped

•

Dual-flash mode, where 8 bits can be sent/received simultaneously by accessing two

flash memories in parallel.

•

SDR and DDR support

•

Fully programmable opcode for both indirect and memory mapped mode

•

Fully programmable frame format for both indirect and memory mapped mode

•

Each of the 5 following phases can be configured independently (enable, length,

single/dual/quad communication)

–

Instruction phase

–

Address phase

–

Alternate bytes phase

–

Dummy cycles phase

–

Data phase

•

Integrated FIFO for reception and transmission

•

8, 16, and 32-bit data accesses are allowed

•

DMA channel for indirect mode operations

•

Programmable masking for external flash flag management

•

Timeout management

•

Interrupt generation on FIFO threshold, timeout, status match, operation complete, and

access error

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