STM32WB55CC datasheet(104/165 Pages) STMICROELECTRONICS

104 / 165 page

Electrical characteristics

STM32WB55xx

104/165

DS11929 Rev 3

6.3.9

Wakeup time from Low-power modes and voltage scaling

transition times

The wakeup times given in Table 49 are the latency between the event and the execution of

the first user instruction.

The device goes in Low-power mode after the WFE (Wait For Event) instruction.

APB2

AHB to APB2(4)

1.10

0.885

1.35

µA/MHz

TIM1

8.20

6.80

7.25

TIM17

TBD

TIM16

2.75

2.30

2.55

USART1 independent clock domain

TBD

USART1 clock domain

TBD

SPI1

TBD

SAI1 independent clock domain

TBD

SAI1 clock domain

TBD

All APB2 on

TBD

ALL

TBD

µA/MHz

1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).

2. The GPIOx (x= A…H) dynamic current consumption is approximately divided by a factor two vs. the values of this table

when the GPIO port is locked through the LCKK and LCKy bits in the GPIOx_LCKR register. To save the full GPIOx current

consumption, the GPIOx clock needs to be disabled in the RCC when all port I/Os are used in alternate function or analog

mode (clock is only required to read or write into GPIO registers, and is not used in AF or analog modes).

3. The AHB to APB1 bridge is automatically active when at least one peripheral is ON on the APB1.

4. The AHB to APB2 bridge is automatically active when at least one peripheral is ON on the APB2.

Table 48. Peripheral current consumption (continued)

Peripheral

Range 1

Range 2

Low-power

run and sleep

Unit

Table 49. Low-power mode wakeup timings(1)

Symbol

Parameter

Conditions

Typ

Max

Unit

tWUSLEEP

Wakeup time from

Sleep mode

to Run mode

-9

No. of

CPU

cycles

tWULPSLEEP

Wakeup time from

Low-power sleep mode

to Low-power run mode

Wakeup in Flash with memory in power-down

during low-power sleep mode (FPDS = 1 in

PWR_CR1) and with clock MSI = 2 MHz

910

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