GD9FS1G8F2AMG datasheet(16/55 Pages) GIGADEVICE

Nome de Peças	GD9FS1G8F2AMG

Descrição Electrónicos	Single level cell technology

PDF	55 Pages

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Fabricante Electrônico	GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]

Página de início	http://www.gigadevice.com/

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GD9Fx1GxF2A

7.3 Data Input Cycle

Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serially and timed

by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command Latch

Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enable.

DIN0

CLE

CE#

ALE

WE#

I/Ox

tCLS

tCS

tALS

tWC

tWP

tWH

tALH

tCH

tCLH

DIN1

DINn

tCH

tDS

tDH

Figure 11: Data Input Cycle figures

7.4 Data Output Cycle

Data Output bus operation allows to output data from the device. The data output cycle is serially and timed by the Read

Enable cycles.

Data output may be used with CE# don’t care. However, if CE# don’t care is used tCEA and tCOH timing

requirements shall be met by the host.

DOUT0

DOUT1

DOUTn

tRR

tCEA

tRP

tREH

tRHOH

tCOH

tCHZ

CE#

RE#

R/B#

I/Ox

tRC

tRHZ

tREA

tRHZ

Figure 12_a: Data Output Cycle figures

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