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DSP56857 Folha de dados(PDF) 65 Page - Freescale Semiconductor, Inc |
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DSP56857 Folha de dados(HTML) 65 Page - Freescale Semiconductor, Inc |
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65 / 662 page ![]() Peripheral Descriptions 5685X Overview, Rev. 4 Freescale Semiconductor 1-33 • Boot mode control • Memory map control • External I/O configuration SIM features include: • Four system bus clocks with pipeline hold off support at master clock frequency/2 • Three system clocks for non pipelined interfaces at master clock frequency/2 • A peripheral bus (IPBus) clock, both on standard and inverted versions at master clock frequency/4 • An external clock output with disable at master clock frequency/5 • A core stall control used to stall the 56800E core system clock for DMA mastership • Three power modes to control power utilization • Controls to enable/disable the 56800E core Wait and Stop instructions • Software initiated reset • Controls to redirect internal data and/or program RAM accesses to the external memory interface • Software Boot mode Control Register, initialized at any reset except COP reset from external pads via SIM inputs MODEA, B, and C • A hold off output to coordinate system and peripheral buses • Two 16-bit registers reset only by a power-on reset usable for general purpose software control 1.12.11 JTAG/Enhanced OnCE Port The JTAG/Enhanced OnCE port allows insertion of the 5685x devices into a target system while retaining debug control. The JTAG port provides board-level testing capability for scan-based emulation compatible with the IEEE 1149.1a-1993 IEEE Standard Test Access Port and Boundary Scan Architecture specification defined by the JTAG. Five dedicated pins interface to a TAP containing a 16-state controller. The EOnCE module allows the user to interact in a debug environment with the 56800E core and its peripherals nonintrusively. Its capabilities include: • Examining registers, memory, or on-chip peripherals • Setting breakpoints in memory • Stepping or tracing instructions |
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