DSP56857 datasheet(21/662 Pages) FREESCALE

21 / 662 page

LIST OF TABLES

List of Tables, Rev. 4

xix

Freescale Semiconductor

0-1

Pin Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxix

1-1

Feature Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

2-1

Functional Group Pin Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2-2

Power Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2-3

Grounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2-4

External Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2-5

External Chip Select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2-6

Host Interface Eight. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2-7

Quad Timer Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2-8

Interrupt and Program Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2-9

Serial Communication Interface 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2-10

Serial Communication Interface 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2-11

Enhanced Synchronous Serial Interface 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2-12

Enhanced Synchronous Serial Interface 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2-13

Serial Peripheral Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2-14

Clock and Phase Lock Loop Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2-15

JTAG/EOnCE Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

3-1

EOnCE Memory Map (EOnCE_BASE = $FFFF00) . . . . . . . . . . . . . . . . . . . . . . . . 3-9

3-2

System Integration Module Register Address Map

(SYS_BASE = $1FFF08) see Chapter 4 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

3-3

External Memory Interface Registers Address Map

(EMI_BASE = $1FFE40) see Chapter 5 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

3-4

Clock Generation Module Registers Address Map

(CGM_BASE = $1FFF10) see Chapter 6 . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

3-5

Computer Operating Properly Module Registers Address Map

(COP_BASE = $1FFFD0) see Chapter 7. . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

3-6

Interrupt Control Registers Address Map

(ITCN_BASE = $1FFF20) see Chapter 8. . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

3-7

Direct Memory Access 0 Register Address Map

(DMA0_BASE = $1FFEC0) see Chapter 9 . . . . . . . . . . . . . . . . . . . . . . . . 3-12

3-8

Direct Memory Access 1 Register Address Map

(DMA1_BASE = $1FFEC8) see Chapter 9 . . . . . . . . . . . . . . . . . . . . . . . . 3-12

3-9

Direct Memory Access 2 Register Address Map

(DMA2_BASE = $1FFED0) see Chapter 9 . . . . . . . . . . . . . . . . . . . . . . . . 3-12

3-10

Direct Memory Access 3 Register Address Map

(DMA3_BASE = $1FFED8) see Chapter 9 . . . . . . . . . . . . . . . . . . . . . . . . 3-13

3-11

Direct Memory Access 4 Register Address Map

(DMA4_BASE = $1FFEE0) see Chapter 9 . . . . . . . . . . . . . . . . . . . . . . . . 3-13

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