AD5669RBCBZ-1-R5 datasheet(22/30 Pages) AD

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AD5629R/AD5669R

Data Sheet

Rev. F | Page 22 of 30

OUTPUT AMPLIFIER

The output buffer amplifier can generate rail-to-rail voltages on

its output, which gives an output range of 0 V to VDD. The amplifier

is capable of driving a load of 2 kΩ in parallel with 1000 pF to

GND. The source and sink capabilities of the output amplifier

can be seen in Figure 25 and Figure 26. The slew rate is 1.5 V/µs

with a ¼ to ¾ scale settling time of 10 µs.

SERIAL INTERFACE

The AD5629R/AD5669R have 2-wire I2C-compatible serial

interfaces (refer to The I2

C-Bus Specification, Version 2.1,

January 2000, available from Philips Semiconductor). The

AD5629R/AD5669R can be connected to an I2C bus as a slave

device under the control of a master device. See Figure 2 for a

timing diagram of a typical write sequence.

The AD5629R/AD5669R support standard (100 kHz) and fast

(400 kHz) modes. High speed operation is only available on

selected models. See the Ordering Guide for a full list of

models. Support is not provided for 10-bit addressing and

general call addressing.

The AD5629R/AD5669R each have a 7-bit slave address. The

parts have a slave address whose five MSBs are 10101, and the

two LSBs are set by the state of the A0 address pin, which

determines the state of the A0 and A1 address bits.

The facility to make hardwired changes to the A0 pin allows the

user to incorporate up to three of these devices on one bus, as

outlined in Table 7.

Table 7. ADDR Pin Settings

A0 Pin Connection

VDD

GND

The 2-wire serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a start

condition when a high-to-low transition on the SDA line

occurs while SCL is high. The following byte is the address

byte, which consists of the 7-bit slave address. The slave

address corresponding to the transmitted address responds

by pulling SDA low during the ninth clock pulse (this is

termed the acknowledge bit). At this stage, all other devices

on the bus remain idle while the selected device waits for

data to be written to or read from its shift register.

2. Data is transmitted over the serial bus in sequences of nine

clock pulses (eight data bits followed by an acknowledge

bit). The transitions on the SDA line must occur during

the low period of SCL and remain stable during the high

period of SCL.

3. When all data bits have been read or written, a stop

condition is established. In write mode, the master pulls

the SDA line high during the 10th clock pulse to establish

a stop condition. If a stop condition is generated between

the 7th and 8th clock pulse of the I2C address frame, a power

cycle is required to recover the part. In read mode, the master

issues a no acknowledge for the ninth clock pulse (that is,

the SDA line remains high). The master brings the SDA

line low before the 10th clock pulse and then high during

the 10th clock pulse to establish a stop condition.

WRITE OPERATION

When writing to the AD5629R/AD5669R, the user must begin

with a start command followed by an address byte (R/W = 0),

after which the DAC acknowledges that it is prepared to receive

data by pulling SDA low. The AD5629R/AD5669R require two

bytes of data for the DAC and a command byte that controls

various DAC functions. Three bytes of data must, therefore, be

written to the DAC, the command byte followed by the most

significant data byte and the least significant data byte, as shown in

Figure 51. After these data bytes are acknowledged by the

AD5629R/AD5669R, a stop condition follows.

READ OPERATION

When reading data back from the AD5629R/AD5669R, the

user begins with a start command followed by an address byte

(R/W = 1), after which the DAC acknowledges that it is prepared

to transmit data by pulling SDA low. Three bytes of data are then

read from the DAC, the first two of which are both acknowledged

by the master as shown in Figure 52. A stop condition follows.

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