Data Sheet

AD5629R/AD5669R

Rev. F | Page 7 of 30

Table 4.

Parameter

Conditions

Min

Max

Unit

Description

Standard mode

100

kHz

Serial clock frequency

Fast mode

400

kHz

Standard mode

4

μs

Fast mode

0.6

μs

Standard mode

4.7

μs

Fast mode

1.3

μs

Standard mode

250

ns

Fast mode

100

ns

Standard mode

0

3.45

μs

Fast mode

0

0.9

μs

Standard mode

4.7

μs

Fast mode

0.6

μs

Standard mode

4

μs

Fast mode

0.6

μs

Standard mode

4.7

μs

Fast mode

1.3

μs

Standard mode

4

μs

Fast mode

0.6

μs

Standard mode

1000

ns

Fast mode

300

ns

Standard mode

300

ns

Fast mode

300

ns

Standard mode

1000

ns

Fast mode

300

ns

Standard mode

1000

ns

after an acknowledge bit

Fast mode

300

ns

Standard mode

300

ns

Fast mode

300

ns

Standard mode

10

ns

LDAC pulse width low

Fast mode

10

ns

Standard mode

300

ns

Falling edge of ninth SCL clock pulse of last byte of a valid write to

the LDAC falling edge

Fast mode

300

ns

Standard mode

20

ns

CLR pulse width low

Fast mode

20

ns

Fast mode

0

50

ns

Pulse width of spike suppressed

1

The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on the EMC

behavior of the part.

2

Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode or less than 10 ns for high speed mode.