MC33593

MOTOROLA SEMICONDUCTORS PRODUCTS

22

revision 7.0, 5 February 2002

© Motorola, Inc., 2002.

4

PLL Divider & Crystal Oscillator

4.1

Maximum Crystal

Series Resistance

--

200

Ω

5

Data Filter & Slicer, Data Manager, SPI

5.1

Data Frequency

OOK and FSK modulations, DME=0

1

-

11

kHz

5.2

Low pass filter delay

2nd order Butterworth response

DR1=0, DR0=0, 1200 bauds

51

73

102

µs

5.3

DR1=0, DR0=1, 2400 bauds

30

42

57

µs

5.4

DR1=1, DR0=0, 4800 bauds

19

25

34

µs

5.5

DR1=1, DR0=1, 9600 bauds

12

16

22

µs

5.6

Data Rate Range

for Clock Recovery

DR1=0, DR0=0

1.0

-

1.4

kBd

5.7

DR1=0, DR0=1

2

-

2.7

kBd

5.8

DR1=1, DR0=0

4

-

5.3

kBd

5.9

DR1=1, DR0=1

8.6

-

10.6

kBd

5.10

Input Low Voltage

Pins MOSI, SCLK, RESETB

0

-

0.3

×

V

5.11

Input High Voltage

0.7

×

-

V

5.13

Input Pull Down Current

-2

-

µA

5.14

Output Low Voltage

Pins MOSI, MISO, SCLK,

00.02

0.2

×

V

5.15

Output High Voltage

0.8

×

4.97

V

5.16

Fall/Rise Time

from 10% to 90% of the output swing

--

100

ns

5.17

Input Low Voltage

Pin STROBE used as digital input

0-

0.5

V

5.18

Input High Voltage

4.4

-

V

5.19

Input Pull Down Current

Pin STROBE used as digital input,

--

50

µA

5.20

SPI data rate

On MOSI, MISO & SCLK,

SPI master or slave,

see note 8

--

310

kBd

5.21

SPI interface source current

CC

MOSI, MISO, SCLK pins

60

170

-

µA

5.22

SPI interface sink current

CC

60

220

-

µA

Note 8: As well as the state machine, the SPI interface is synchronized by a sampling clock at 615kHz derivated

from the crystal oscillator. The maximum speed is then half this synchronization clock.

ELECTRICAL CHARACTERISTICS

the circuit in recommended in the application schematic (see figure 17), unless otherwise specified. Typical

Parameter

Test Conditions, Comments

Limits

Unit

Min.

Typ.

Max.

Freescale Semiconductor, Inc.

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