LTC6955 datasheet(4/22 Pages) AD

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LTC6955

Rev 0

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VD+ = VIN+ = VOUT+ = 3.3V unless otherwise specified (Note 2).

All voltages are with respect to GND.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Power Supply Voltages

VOUT+ Supply Range

3.15

3.3

3.45

VD+ Supply Range

3.15

3.3

3.45

VIN+ Supply Range

3.15

3.3

3.45

Power Supply Currents

IDDOUT

LTC6955 VOUT+ Supply Current

(Note 3)

SEL = 14, All Outputs Active

350

420

SEL = 1, Three Outputs Active

105

SEL = 0 or 15, All Outputs Off

µA

LTC6955-1 VOUT+ Supply Current

(Note 3)

SEL = 14, All Outputs Active

358

430

SEL = 1, Three Outputs Active

108

SEL = 0 or 15, All Outputs Off

µA

IDD – 3.3V

LTC6955 or LTC6955-1 Sum VD+,

VIN+ Supply Currents (Note 3)

SEL = 14, All Outputs Active

110

SEL = 1, Three Outputs Active

SEL = 0, All Outputs Off, Temp Diode Off

µA

SEL = 15, All Outputs Off, Temp Diode On

360

µA

Additive Phase Noise, Jitter and Spurious (Note 5)

Output Noise/Jitter, fIN = 7.5GHz

Phase Noise Floor

–155.2

dBc/Hz

RMS Jitter, 12kHz to 20MHz Integration BW

fsRMS

RMS Jitter, ADC SNR Method (Note 6)

fsRMS

Output Noise/Jitter, fIN = 1.0GHz

Phase Noise Floor

–164

dBc/Hz

RMS Jitter, 12kHz to 20MHz Integration BW

fsRMS

RMS Jitter, ADC SNR Method (Note 6)

fsRMS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTC6955 is guaranteed to meet specified performance limits

over the full operating junction temperature range of –40°C to 125°C.

Note 3: The SEL code (SEL) programs the state of each output as

described in Table 2. SEL’s value is determined by the voltage state of the

SELx pins. If VSELx > VIH, its digital value (SELx) is “1”. If VSELx < VIL, its

digital value (SELx) is “0”. The SEL code is equal to 8 • SEL3 + 4 • SEL2 +

2 • SEL1 + SEL0.

Note 4: For LTC6955, skew is defined as the difference between the zero-

crossing time of a given output and the average zero-crossing time of all

outputs. For LTC6955-1, skew is defined as the difference between the

zero-crossing time of a given output and the average zero-crossing time of

outputs 0 to 9.

Note 5: Additive phase noise and jitter from LTC6955 only. Incoming clock

phase noise is not included.

Note 6: Additive RMS jitter (ADC SNR method) is calculated by integrating

the distribution section’s measured additive phase noise floor out to fCLK.

Actual ADC SNR measurements show good agreement with this method.

Note 7: The LTC6955 is driven from a VCO (CVCO55CC-4000-4000)

through a splitter. The other side of the splitter drives the input of a

LTC6952 to lock the VCO in a PLL. The reference for the LTC6952 PLL is a

Pascal OCXO-E, fREF = 100MHz, PREF = 6dBm.

Note 8: Measured using DC2611.

Note 9: Cable loss is de-embeded in this plot, but board and connector

losses are not. Output board traces are approximately 5cm long.

Note 10: Data for outputs 0 to 9 was taken on 1304 total parts from four

assembly lots (two LTC6955 and two LTC6955-1). Data for LTC6955

OUT10 was taken on 710 parts from two assembly lots. Data for

LTC6955-1 OUT10 was taken on 594 parts from two assembly lots.

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