LTC6652 datasheet(36/50 Pages) LINER

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LTC2373-18

237318f

For more information www.linear.com/LTC2373-18

Figure 24. MUX Reset Timing

MUX Reset Timing

The parasitic capacitances (CPAR) on the output summing

nodes of the MUX, MUXOUT+/–, are discharged to ground

every conversion cycle and when a first new valid con-

figuration word is programmed into the sequencer. This

is done to avoid crosstalk between input channels due to

charge sharing from CPAR. The bottom most waveform in

Figure24representsthevoltagesoftheMUXoutputnodes.

The MUX is being reset when V(MUXOUT+/–) sits at 0V.

The MUX turns OFF and begins resetting tCNVMRST ns

after a conversion is initiated by the rising edge of CNV.

After tMRST1 ns, the MUX turns ON to the next channel

programmed in the sequencer.

The MUX also turns OFF and resets after tVLDMRSTnswhen

afirstnewvalidconfigurationwordisprogrammedintothe

sequencer on the 8th rising edge of SCK. This is because

the MUX may need to switch channels based on the newly

input configuration, so memory of the previous channel

needs to be cleared. A new acquisition period begins when

the MUX is reconnected after tMRST2 ns.

TiMing DiagraMs

CNV

BUSY

V(MUXOUT+/–)

tMRST1

tCNVMRST

SCK

SDO

237318 F24

D17 D16

D15

D14

D13

D12 D11

D10

SOS

SDI

C[7] C[6] C[5]

C[4]

C[3] C[2] C[1] C[0]

tVLDMRST

tMRST2

tACQ

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