AT89C5130A-RDTIM datasheet(137/184 Pages) ATMEL

137 / 184 page

137

AT89C5130A/31A-M

4337C–USB–02/05

USB Registers

Table 94. USBCON Register

USBCON (S:BCh)

USB Global Control Register

Reset Value = 00h

765

43210

USBE

SUSPCLK

SDRMWUP

DETACH

UPRSM

RMWUPE

CONFG

FADDEN

Bit Number

Bit Mnemonic

Description

7USBE

USB Enable

Set this bit to enable the USB controller.

Clear this bit to disable and reset the USB controller, to disable the USB

transceiver an to disable the USB controller clock inputs.

6SUSPCLK

Suspend USB Clock

Set this bit to disable the 48 MHz clock input (Resume Detection is still

active).

Clear this bit to enable the 48 MHz clock input.

SDRMWUP

Send Remote Wake Up

Set this bit to force an external interrupt on the USB controller for Remote

Wake UP purpose.

An upstream resume is send only if the bit RMWUPE is set, all USB clocks

are enabled AND the USB bus was in SUSPEND state for at least 5 ms.

See UPRSM below.

This bit is cleared by software.

DETACH

Detach Command

Set this bit to simulate a Detach on the USB line. The V

REF pin is then in a

floating state.

Clear this bit to maintain VREF at high level.

3UPRSM

Upstream Resume (read only)

This bit is set by hardware when SDRMWUP has been set and if RMWUPE

is enabled.

This bit is cleared by hardware after the upstream resume has been sent.

2RMWUPE

Remote Wake-Up Enable

Set this bit to enabled request an upstream resume signaling to the host.

Clear this bit otherwise.

Note: Do not set this bit if the host has not set the

DEVICE_REMOTE_WAKEUP feature for the device.

1CONFG

Configured

This bit will be set by the device firmware after a SET_CONFIGURATION

request with a non-zero value has been correctly processed.

It will be cleared by the device firmware when a SET_CONFIGURATION

request with a zero value is received. It is cleared by hardware on hardware

reset or when an USB reset is detected on the bus (SE0 state for at least 32

Full Speed bit times: typically 2.7

µs).

FADDEN

Function Address Enable

This bit will be set by the device firmware after a successful status phase of

a SET_ADDRESS transaction.

It will not be cleared afterwards by the device firmware. It is cleared by

hardware on hardware reset or when an USB reset is received (see above).

When this bit is cleared, the default function address is used (0).

AT89C5130A-RDTIM Folha de dados(PDF) 137 Page - ATMEL Corporation

AT89C5130A-RDTIM Folha de dados(HTML) 137 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL