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LED171596ARSLR Folha de dados(PDF) 13 Page - Texas Instruments |
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LED171596ARSLR Folha de dados(HTML) 13 Page - Texas Instruments |
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13 / 153 page ![]() LED Driver 0 LED Driver 23 HS Switch 0 HS Switch 3 LED0 LED23 HS0 HS3 TSD OSC IOs SRAM LOGIC EPROM VLED LED_GND ISET VDD GND VDDIO EN IFSEL_LATCH SCLK_SCL MISO_ADDR MOSI_SDA SS_PWM INT GND GND GND GND GND GND GND EPAD Copyright © 2016, Texas Instruments Incorporated 13 LED171596A www.ti.com SNVSAY2 – OCTOBER 2017 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Control Interface Register control interface is selected with IFSEL pin according to Table 1. Table 1. Serial Control Interface Selection IFSEL PIN SERIAL INTERFACE VDDIO (1) I2C-compatible GND (0) SPI The SPI interface of the LED171596A device supports up to 10 MHz using a 16-bit register addressing. In I2C mode it supports up to 1-MHz fast-mode-plus specification. The I2C and SPI interfaces are available to use after tEN , following the rising edge of the EN pin. Following start-up and IFSEL detection (tIFSEL_HOLD max), the LATCH pin functionality is enabled to start SRAM buffer updates. The LATCH pulse duration must be at least tLATCH ns. Alternatively, the LATCH register bit can also be used. |
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