AD9200_17 datasheet(9/25 Pages) AD

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AD9200

–8–

REV. E

Table I. Mode Selection

Input

MODE

REFSENSE

Modes

Connect

Span

REF

REFTS

REFBS

Figure

TOP/BOTTOM

AIN

1 V

AVDD

Short REFSENSE, REFTS and VREF Together

AGND

AIN

2 V

AVDD

AGND

Short REFTS and VREF Together

AGND

CENTER SPAN

AIN

1 V

AVDD/2

Short VREF and REFSENSE Together

AVDD/2

AIN

2 V

AVDD/2

AGND

No Connect

AVDD/2

Differential

AIN Is Input 1

1 V

AVDD/2

Short VREF and REFSENSE Together

AVDD/2

REFTS and

REFBS Are

Shorted Together

for Input 2

2 V

AVDD/2

AGND

No Connect

AVDD/2

External Ref

AIN

2 V max AVDD

AVDD

No Connect

Span = REFTS

21, 22

– REFBS (2 V max)

AGND

Short to

VREFTF

VREFBF

AD876

AIN

2 V

Float or

AVDD

No Connect

Short to

AVSS

VREFTF

VREFBF

–9

1.0E+6

1.0E+9

10.0E+6

100.0E+6

–3

–6

FREQUENCY – Hz

–12

–15

–18

–21

–24

–27

Figure 13. Full Power Bandwidth

–25

3.0

1.0

2.0

–5

–10

–15

INPUT VOLTAGE – V

–20

2.5

0.5

1.5

REFBS = 0.5V

REFTS = 2.5V

CLOCK = 20MHz

Figure 14. Input Bias Current vs. Input Voltage

APPLYING THE AD9200

THEORY OF OPERATION

The AD9200 implements a pipelined multistage architecture to

achieve high sample rate with low power. The AD9200 distrib-

utes the conversion over several smaller A/D subblocks, refining

the conversion with progressively higher accuracy as it passes

the results from stage to stage. As a consequence of the distrib-

uted conversion, the AD9200 requires a small fraction of the

1023 comparators used in a traditional flash type A/D. A

sample-and-hold function within each of the stages permits the

first stage to operate on a new input sample while the second,

third and fourth stages operate on the three preceding samples.

OPERATIONAL MODES

The AD9200 is designed to allow optimal performance in a

wide variety of imaging, communications and instrumentation

applications, including pin compatibility with the AD876 A/D.

To realize this flexibility, internal switches on the AD9200 are

used to reconfigure the circuit into different modes. These modes

are selected by appropriate pin strapping. There are three parts

of the circuit affected by this modality: the voltage reference, the

reference buffer, and the analog input. The nature of the appli-

cation will determine which mode is appropriate: the descrip-

tions in the following sections, as well as the Table I should

assist in picking the desired mode.

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