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89LPC925 Folha de dados(PDF) 44 Page - NXP Semiconductors |
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89LPC925 Folha de dados(HTML) 44 Page - NXP Semiconductors |
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44 / 49 page ![]() Philips Semiconductors P89LPC924/925 8-bit microcontrollers with accelerated two-clock 80C51 core Product data Rev. 03 — 15 December 2004 44 of 49 9397 750 14471 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Fig 12. Shift register mode timing. 0 1 23 45 6 7 Valid Valid Valid Valid Valid Valid Valid Valid tXLXL 002aaa425 Set TI Set RI tXHQX tQVXH tXHDV tXHDX Clock Output Data Write to SBUF Input Data Clear RI Fig 13. External clock timing. tCHCL tCLCX tCHCX tC tCLCH 002aaa416 0.2 VDD + 0.9 0.2 VDD - 0.1 V VDD - 0.5 V 0.45 V Table 11: AC characteristics, ISP entry mode VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = −40 °Cto+85 °C for industrial, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit tVR RST delay from VDD active 50 - - µs tRH RST HIGH time 1 - 32 µs tRL RST LOW time 1 - - µs Fig 14. ISP entry waveform. 002aaa426 VDD RST tRL tVR tRH |
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