2 / 7 page  CY29949 Document #: 38-07289 Rev. *D Page 2 of 7 Note: 1. PD = internal pull-down, PU = internal pull-up. Pin Description[1] Pin Name PWR I/O Description 6 PECL_CLK I, PD PECL Input Clock 7 PECL_CLK# I, PU PECL Input Clock 4, 5 TCLK(0,1) I, PU External Reference/Test Clock Input 49, 51 QA(1,0) VDDC O Clock Outputs 42, 44, 46 QB(2:0) VDDC O Clock Outputs 31, 33, 35, 37 QC(3:0) VDDC O Clock Outputs 16, 18, 20, 22, 24, 28 QD(5:0) VDDC O Clock Outputs 9, 10, 11, 12 DSEL(A:D) I, PD Divider Select Inputs. When HIGH, selects ÷2 input divider. When LOW, selects ÷1 input divider. 2 TCLK_SEL I, PD TCLK Select Input. When LOW, TCLK0 clock is selected and when HIGH TCLK1 is selected. 8 PCLK_SEL I, PD PECL Select Input. When HIGH, PECL clock is selected and when LOW TCLK(0,1) is selected 1 MR/OE# I, PD Output Enable Input. When asserted LOW, the outputs are enabled and when asserted HIGH, internal flip-flops are reset and the outputs are three-stated. If more than 1 bank is being used in /2 mode, a reset must be performed (MR/OE# asserted high) after power-up to ensure that all internal flip flops are set to the same state. 17, 21, 25, 32, 36, 41, 45, 50 VDDC 2.5V or 3.3V Power Supply for Output Clock Buffers 3VDD 2.5V or 3.3V Power Supply 13, 15, 19, 23, 29, 30, 34, 38, 43, 47, 48, 52 VSS Common Ground 14, 26, 27, 39, 40, NC Not Connected |
|
Portuguese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
