TAS3001CPWR datasheet(17/56 Pages) TI

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2−3

tc(SCLK)

td(SLR)

tr(SCLK)

tf(SCLK)

td(SDOUT)

td(SLR)

tsu(SDIN)

th(SDIN)

SCLK

LRCLK

SDOUT1

SDOUT2

SDOUT0

SDIN1

SDIN2

Figure 2−2. For Right/Left Justified, I2S, Left/Left Justified Serial Protocols

2.1.2

Left-Justified Serial Format

The following are characteristics of this protocol:

•

LRCLK is the left/right clock. The left channel is transmitted when LRCLK is high. The right channel is

transmitted when LRCLK is low.

•

The SDIN data is justified to the leading edge of LRCLK.

•

The MSBs are transmitted at the same time as the LRCLK edge and captured at the very next rising edge

of SCLK.

•

Serial data is sampled into the device on the rising edge of SCLK.

•

Serial data is transmitted out of the device on the falling edge of SCLK.

•

SCLK = 32

× LRCLK (32 × fs SCLK is only supported for 16-bit data) or 64 × LRCLK

•

In this mode, LRCLK does not have to be a 50% duty-cycle clock. The number of bits used in the interface

sets the minimum duty cycle. There must be enough SCLK pulses to shift all of the data.

MSB

LSB

Left Channel

Right Channel

SDIN

SCLK

SDOUT

LRCLK = fs

LSB

Figure 2−3. Left-Justified Serial Format

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