WM8950 datasheet(39/60 Pages) CIRRUS

39 / 60 page

WM8950

Rev 4.5

AUDIO INTERFACE CONTROL

The register bits controlling audio format, word length and master / slave mode are summarised

below. Each audio interface can be controlled individually.

and FRAME are outputs. The frequency of BCLK and FRAME in master mode are controlled with

BCLKDIV. These are divided down versions of master clock. This may result in short BCLK pulses at

the end of a frame if there is a non-integer ratio of BCLKs to FRAME clocks.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Clock

generation

control

Sets the chip to be master over FRAME

and BCLK

0=BCLK and FRAME clock are inputs

1=BCLK and FRAME clock are outputs

generated by the WM8950 (MASTER)

4:2

BCLKDIV

000

Configures the BCLK and FRAME output

frequency, for use when the chip is master

over BCLK.

000=divide by 1 (BCLK=MCLK)

001=divide by 2 (BCLK=MCLK/2)

010=divide by 4

011=divide by 8

100=divide by 16

101=divide by 32

110=reserved

111=reserved

7:5

MCLKDIV

010

Sets the scaling for either the MCLK or

PLL clock output (under control of

CLKSEL)

000=divide by 1

001=divide by 1.5

010=divide by 2

011=divide by 3

100=divide by 4

101=divide by 6

110=divide by 8

111=divide by 12

CLKSEL

Controls the source of the clock for all

internal operation:

0=MCLK

1=PLL output

Table 32 Clock Control

COMPANDING

The WM8950 supports A-law and

-law companding. Companding can be enabled on the ADC

audio interface by writing the appropriate value to the ADC_COMP register bit.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Companding

control

2:1

ADC_COMP

ADC companding

00=off

01=reserved

10=µ-law

11=A-law

Table 33 Companding Control

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