HT86AR72 datasheet(45/68 Pages) HOLTEK

45 / 68 page

HT86Axx/HT86ARxx

Rev. 1.10

December 12, 2012

PCR2

PCR1

PCR0

3210

PC3

PC2

PC1

PC0

PC3

PC2

PC1

AN0

PC3

PC2

AN1

AN0

PC3

AN2

AN1

AN0

AN3

AN2

AN1

AN0

PCR Table: Port A/D Channel Configuration Table

fOSC

A/D Clock Period (tAD)

ADCS1, ADCS0=01

(fOSC/2)

ADCS1, ADCS0=10

(fOSC/8)

ADCS1, ADCS0=00

(fOSC/32)

ADCS1, ADCS0=11

4MHz

500ns

ms8ms

6MHz

333ns

1.3

5.3

8MHz

250ns

ms4ms

A/D Clock Period Examples

A C S R R e g i s t e r

S e l e c t A / D c o n v e r t e r c l o c k s o u r c e

b 7

b 0

T E S T

A D C S 1 A D C S 0

A D C S 1

A D C S 0

: f O S C / 2

: f O S C / 8

: f O S C / 3 2

: N o t i m p l e m e n t e d

N o t i m p l e m e n t e d , r e a d a s " 0 "

F o r t e s t m o d e u s e o n l y

ACSR Register

A/D Input Pins

All of the A/D analog input pins are pin-shared with the

I/O pins on Port C. Bits PCR2~PCR0 in the ACSR regis-

ters, not configuration options, determine whether the

input pins are setup as normal Port C input/output pins

or whether they are setup as analog inputs. In this way,

pins can be changed under program control to change

their function from normal I/O operation to analog inputs

and vice versa. Pull-high resistors, which are setup

through configuration options, apply to the input pins

only when they are used as normal I/O pins, if setup as

A/D inputs the pull-high resistors will be automatically

disconnected. Note that it is not necessary to first setup

the A/D pin as an input in the PBC port control register to

enable the A/D input, when the PCR2~PCR0 bits en-

able an A/D input, the status of the port control register

will be overridden.

The VDD power supply pin is used as the A/D converter

reference voltage, and as such analog inputs must not

be allowed to exceed this value. Appropriate measures

should also be taken to ensure that the VDD pin remains

as stable and noise free as possible.

Initialising the A/D Converter

The internal A/D converter must be initialised in a spe-

cial way. Each time the Port C A/D channel selection bits

are modified by the program, the A/D converter must be

re-initialised. If the A/D converter is not initialized after

the channel selection bits are changed, the EOCB flag

may have an undefined value, which may produce a

false end of conversion signal. To initialize the A/D con-

verter after the channel selection bits have changed,

then, within a time frame of one to ten instruction cycles,

the START bit in the ADCR register must first be set high

and then immediately cleared to zero. This will ensure

that the EOCB flag is correctly set to a high condition.

Summary of A/D Conversion Steps

The following summarizes the individual steps that

should be executed in order to implement an A/D con-

version process.

· Step 1

Select the required A/D conversion clock by correctly

programming bits ADCS1 and ADCS0 in the ACSR

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