S3A3 datasheet(64/139 Pages) RENESAS

64 / 139 page

R01DS0307EU0100 Rev.1.00

Page 64 of 139

Mar 7, 2017

S3A3

2. Electrical Characteristics

2.3.4

Wakeup Time

Note 1.

The division ratio of ICK, BCK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The

recovery time is determined by the system clock source.

Note 2.

The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.

Note 3.

The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.

Note 4.

The HOCO Clock Wait Control Register (HOCOWTCR) is set to 05h.

Note 5.

The HOCO Clock Wait Control Register (HOCOWTCR) is set to 06h.

Note 1.

The division ratio of ICK, BCK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The

recovery time is determined by the system clock source.

Note 2.

The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.

Note 3.

The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.

Table 2.24

Timing of recovery from low power modes (1)

Parameter

Symbol Min

Typ

Max

Unit

Test

conditions

Recovery time

from Software

Standby mode*1

High-speed

mode

Crystal

resonator

connected to

main clock

oscillator

System clock source is

main clock oscillator

(20 MHz)*2

tSBYMC

-2

Figure 2.36

System clock source is

PLL (48 MHz) with Main

clock oscillator*2

tSBYPC

-2

External clock

input to main

clock oscillator

System clock source is

main clock oscillator

(20 MHz)*3

tSBYEX

-14

μs

System clock source is

PLL (48 MHz) with Main

clock oscillator*3

tSBYPE

-53

μs

System clock source is HOCO*4

(HOCO clock is 32 MHz)

tSBYHO

-43

μs

System clock source is HOCO*4

(HOCO clock is 48 MHz)

tSBYHO

-44

μs

System clock source is HOCO*5

(HOCO clock is 64 MHz)

tSBYHO

-82

110

μs

System clock source is MOCO

tSBYMO

-16

μs

Table 2.25

Timing of recovery from low power modes (2)

Parameter

Symbol Min

Typ

Max

Unit

Test

conditions

Recovery time

from Software

Standby mode*1

Middle-speed

mode

Crystal

resonator

connected to

main clock

oscillator

System clock source is

main clock oscillator

(12 MHz)*2

tSBYMC

-2

Figure 2.36

System clock source is

PLL (24 MHz) with main

clock oscillator*2

tSBYPC

-2

External clock

input to main

clock oscillator

System clock source is

main clock oscillator

(12 MHz)*3

tSBYEX

-2.9

μs

System clock source is

PLL (24 MHz) with main

clock oscillator*3

tSBYPE

-49

μs

System clock source is HOCO (24 MHz)

tSBYHO

-38

μs

System clock source is MOCO

tSBYMO

-3.5

5.5

μs

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