TS4621B datasheet(25/48 Pages) STMICROELECTRONICS

25 / 48 page

TS4621B

Application information

Doc ID 022194 Rev 2

25/48

Application information

4.1

I2C bus interface

In compliance with the I²C protocol, the TS4621B uses a serial bus to control the chip’s

functions with the clock (SCL) and data (SDA) wires. These two lines are bi-directional

(open collector) and require an external pull-up resistor (typically 10 k

Ω). The maximum

clock frequency in fast mode specified by the I²C standard is 400 kHz, which the TS4621B

supports. In this application, the TS4621B is always the slave device and the controlling

microcontroller MCU is the master device.

The slave address of the TS4621B is 1100 000x (C0h).

Table 8 summarizes the pin descriptions for the I²C bus interface.

4.1.1

I²C bus operation

The host MCU can write to the TS4621B control register to control the TS4621B, and read

from the control register to obtain a configuration from the TS4621B. The TS4621B is

addressed by the byte consisting of the 7-bit slave address and the R/W bit.

There are four control registers (Table 10) named CR1 to CR4. In read mode, all the control

registers can be accessed. In write mode, only CR1, CR2 and CR3 can be addressed.

Table 8.

Pin description of the I²C bus interface

Functional description

SDA

Serial data pin

SCL

Clock input pin

Table 9.

First byte after the START message for addressing the device

R/W

000

Table 10.

Summary of control registers

Description

address

CR1

HP_EN_L HP_EN_R

SC_L

SC_R

T_SH

SWS

CR2

volume control

Mute_L

Mute_R

Volume control

CR3

HiZ_L HiZ_R

CR4

identification

TS4621B Folha de dados(PDF) 25 Page - STMicroelectronics

TS4621B Folha de dados(HTML) 25 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Folha de dados Download

Ligação URL