LP3906 Default Power-Off Sequence

20197811

Symbol

Description

Min

Typ

Max

Units

t

1

Programmable Delay from EN_T deassertion to V

1.5

ms

t

2

Programmable Delay from EN_T deassertion to V

2

ms

t

3

Programmable Delay from EN_T deassertion to V

3

ms

t

4

Programmable Delay from EN_T deassertion to V

6

ms

Note: LP3906 The default Power on delays can be reprogrammed at final test to 0, .5, 1, 2, 5, or 10 ms. Default setting is the same as the on sequence.

Power-On-Reset

The LP3906 is equipped with an internal Power-On-Reset

This guarantees that the logic is properly initialized when

VDD rises above the minimum operating voltage of the Logic

and the internal oscillator that clocks the Sequential Logic in

the Control section.

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