A8650 datasheet(21/31 Pages) ALLEGRO

21 / 31 page

Low Input Voltage, Adjustable Frequency

2 A Synchronous Buck Regulator with EN/SYNC and Power OK

A8650

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Input Capacitors

Three factors should be considered when choosing the input

capacitors. First, they must be chosen to support the maximum

expected input voltage with adequate design margin. Second,

their rms current rating must be higher than the expected rms

input current to the regulator. Third, they must have enough

capacitance and a low enough ESR to limit the input voltage

dv/dt to something much less than the hysteresis of the VIN pin

UVLO circuitry (200 mV (typ)) at maximum loading and mini-

mum input voltage.

The input capacitor(s) must limit the voltage deviations at the

VIN pin to something significantly less than the A8650 VIN pin

UVLO hysteresis during maximum load and minimum input

voltage. The minimum input capacitance can be calculated as

follows:

≥

CIN

IOUT

∆VIN(MIN)

fSW

0.85

D (1– D)

(14)

where ΔVIN(MIN) is chosen to be much less than the hysteresis of

the VIN pin UVLO comparator (ΔVIN(MIN) ≤ 100 mV is recom-

mended), and fSW is the nominal PWM output frequency.

The D×(1–D) term in equation 14 has an absolute maximum

value of 0.25 at 50% duty cycle. So, for example, a very con-

servative design, based on: IOUT = 2.0 A, fSW = 85% of 2 MHz,

D × (1–D) = 0.25, and ΔVIN = 100 mV, yields:

≥

CIN

1.7 (MHz) 100 (mV)

2.9 µF

2.0 (A) 0.25

The input capacitors must deliver the rms current according to:

Irms

IOUT D (1– D)

(15)

where the duty cycle D = VOUT/VIN.

Figure 11 shows the normalized input capacitor rms current ver-

sus duty cycle. To use this graph, simply find the operational duty

cycle (D) on the x-axis and determine the input/output current

multiplier on the y-axis. For example, at a 20% duty cycle, the

input/output current multiplier is 0.40. Therefore, if the regula-

tor is delivering 2.0 A of steady-state load current, the input

capacitor(s) must support 0.40 × 2.0 A or 0.8 ARMS.

A good design should consider the DC-bias effect on a ceramic

capacitor. As the applied voltage approaches the rated value, the

capacitance value decreases. This effect is very pronounced with

the Y5V and Z5U temperature characteristic devices (as much as

90% reduction) so these types should be avoided. The X5R and

X7R type capacitors should be the primary choices due to their

stability versus both DC bias and temperature.

For all ceramic capacitors, the DC bias effect is even more

pronounced on smaller case sizes so a good design will use the

largest affordable case size (such as 1206 or 1210). Also, it is

advisable to select input capacitors with plenty of design margin

in the voltage rating to accommodate the worst case transient

input voltage.

Soft Start and Hiccup Mode Timing (CSS)

The soft start time of the A8650 is determined by the value of the

capacitance at the soft start pin, CSS. When the A8650 is enabled

the voltage at the soft start pin will start from 0 V and will be

charged by the soft start current, ISSSU. However, PWM switch-

ing will not begin instantly because the voltage at the soft start

pin must rise above 200 mV. The soft start delay (tSS(DELAY)) can

be calculated using the following equation:

tSS(DELAY) CSS

ISSSU

200 (mV)

(16)

If the A8650 is starting into a very heavy load a very fast soft

start time may cause the regulator to exceed the cycle-by-cycle

overcurrent threshold. This occurs because the total of the full

load current, the inductor ripple current, and the additional cur-

rent required to charge the output capacitors:

ICO = COUT × VOUT / tSS

(17)

0.55

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

100

Duty Cycle (%)

Figure 11. Input capacitor ripple versus duty cycle

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