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L9658 Folha de dados(PDF) 48 Page - STMicroelectronics |
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L9658 Folha de dados(HTML) 48 Page - STMicroelectronics |
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48 / 64 page ![]() Functional description L9658 48/64 Doc ID 14219 Rev 3 4.14.1 Current sensor Each output channel senses the current drawn by the remote satellite sensor; the circuit modulates the load current into logic voltage levels for post processing by a manchester decoder. Each channel has an internal comparator with a programmable currents trip points selectable through the appropriate setting in the CCR Register for each of the 4 satellite channels. The current sense comparator provides a hysteresis, which can be enabled through appropriate setting in the CCR Register. Each comparator output have a de-glitch filter as a function of the protocol speed as defined in the AC characteristic table. Each current is limited to 150 mA maximum and includes a fault timer. If the output for a given channel is in current limited for a period of time exceeding the output fault timer, the IC will report an over current fault via SPI and latch off the affected channel, the channel will remain in latch off mode until the user send a SPI command to re-activate the channel. When the output is shorted to battery, an internal comparator senses the output voltage level then turn off an internal series transistor to provide blocking diode for the current going through the output channel, the output will resume normal operation once the fault condition is removed. The comparator have 20 to 50 mV input offset to prevent turning off the output under an open circuit condition. In case of loss of VCC all output will remain off. 4.14.2 Manchester decoding The L9658 decodes satellite massages based on Manchester decoding, each of the four satellite channels have a Manchester decoder that can be enabled or disabled through the CCR register. An example of Manchester decoding is given below; logic 0 is defined as a signal transition from 0 to 1 at 50 % Duty cycle, logic 1 is defined as a signal transition from 1 to 0 at 50 % duty cycle. The IC starts decoding the satellite message after it receives two SYNC bits defined as logic 00, the SYNC bits are used to determine the bit rate of the incoming message and are used as the time base in decoding the following bits; different bit rates ranges are programmable via SPI, in case the measured bit rate obtained using the 2 SYNC bits doesn’t fall within the range selected by he SPI as defined, the device declares a bit time error, revert to the minimum bit time of the selected range, and wait for idle. Figure 19. Manchester decoding 1 01 0 01 0 Id l e |
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