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STHDLS101T Folha de dados(PDF) 15 Page - STMicroelectronics

Nome de Peças STHDLS101T
Descrição Electrónicos  AC coupled HDMI level shifter with configurable HPD output
PDF  26 Pages
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Fabricante Electrônico  STMICROELECTRONICS [STMicroelectronics]
Página de início  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STHDLS101T Folha de dados(HTML) 15 Page - STMicroelectronics

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STHDLS101T
Maximum ratings
15/26
5.1
Recommended operating conditions
5.1.1
Power supply and temperature range
5.1.2
Differential inputs (IN_D signals)
Table 7.
Power supply and temperature range
Symbol
Parameter
Comments
Min
Typ
Max
Unit
VCC33
3.3 V power supply
3.0
3.3
3.6
V
ICC
Maximum power supply current
Total current from VCC
3.3 V power supply
100
mA
T
Operating temperature range
-40
85
oC
Table 8.
Differential input characteristics for IN_D signals
Symbol
Parameter
Comments
Min
Typ
Max
Unit
Tbit
Unit interval
Tbit is determined by the
display mode. Nominal bit
rate ranges from 250 Mbps
to 2.5 Gbps per lane.
Nominal Tbit at
2.5 Gbps = 400 ps. 360 ps =
400 ps – 10%
360
ps
VRX-DIFFp-p Differential input peak to peak voltage
VRX-DIFFp-p=2*|VRX-D+ - VRX-
D-|. Applies to IN_D signals.
0.175
1.2
V
TRX-EYE
Minimum eye width at IN_D input pair
The level shifter may add a
maximum of 0.02UI jitter
0.8
Tbit
VCM-AC-pp
AC peak common mode input voltage
VCM-AC-pp=|VRX-D+ +
VRX-D-|/2 – VRX-CM-DC.
VRX-CM-DC=DC(avg) of
|VRX-D+ + VRX-D-|/2
VCM-AC-pp includes all
frequencies above 30 kHz.
100
mV
ZRX-DC
DC single-ended input impedance
Applies to IN_D+ as well as
IN_D- pins (50
Ω ± 20%
tolerance)
40
50
60
Ω
VRX-Bias
RX input termination voltage
Intended to limit power-up
stress on chipset’s PCIE
output buffers
02
V
ZRX-HIGH-Z
Single-ended input resistance for
IN_Dx when inputs are in high-Z state
Differential inputs must be in
a high impedance state
100
K
Ω
Obsolete
Product(s)
- Obsolete
Product(s)



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