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HD64646FS Folha de dados(PDF) 42 Page - Hitachi Semiconductor |
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HD64646FS Folha de dados(HTML) 42 Page - Hitachi Semiconductor |
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42 / 50 page ![]() HD64645/64646 42 Electrical Characteristics DC Characteristics (V CC = 5.0V ±10%, GND = 0V, Ta = –20°C to +75°C, unless otherwise noted) Item Symbol Min Typ Max Unit Test Condition Input high voltage RES, MODE, SK0, SK1 VIH V CC – 0.5 V CC + 0.3 V DCLK, ON/ OFF 2.2 V CC + 0.3 V All others 2.0 V CC + 0.3 V Input low voltage All others VIL –0.3 0.8 V Output high TTL interface* 1 VOH 2.4 V I OH = –400 µA voltage CMOS interface* 1 V CC – 0.8 V I OH = –400 µA Output low TTL interface VOL 0.4 V I OL = 1.6 mA voltage CMOS interface 0.8 V I OL = 400 µA Input leakage current All inputs except DB0–DB7 I IL –2.5 +2.5 µA Three state (off-state) leakage current DB0–DB7 I TSL –10 +10 µA Current dissipation* 2 I CC 10 mA Notes: 1. TTL Interface; MA0–MA15, RA0–RA4, DISPTMG, CUDISP, DB0–DB7, MCLK C-MOS Interface; LU0–LU3, LD0–LD3, CL1, CL2, M, FLM 2. Input/output current is excluded. When input is at the intermediate level with CMOS, excessive current flows through the input circuit to power supply. Input level must be fixed at high or low to avoid this condition. 3. If the capacitive loads of LU0–LU3 and LD0–LD3 exceed the rating, noise over 0.8 V may be produced on CUDISP, DISPTMG, MCLK, FLM and M. In case the loads of LU0–LU3 and LD0– LD3 are larger than the ratings, supply signals to the LCD module through buffers. |
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