STM8L151F3 datasheet(98/122 Pages) STMICROELECTRONICS

98 / 122 page

Electrical parameters

STM8L151x2, STM8L151x3

98/122

DocID018780 Rev 9

Figure 37. ADC1 accuracy characteristics

Figure 38. Typical connection diagram using the ADC1

1. Refer to Table 48 for the values of RAIN and CADC1.

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy

this, fADC1 should be reduced.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 39 or Figure 40,

depending on whether VREF+ is connected to VDDA or not. Good quality ceramic 10 nF

capacitors should be used. They should be placed as close as possible to the chip.

1LSBIDEAL

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) End point correlation line

ET=Total Unadjusted Error: maximum deviation

between the actual and the ideal transfer curves.

EO=Offset Error: deviation between the first actual

transition and the first ideal one.

EG=Gain Error: deviation between the last ideal

transition and the last actual one.

ED=Differential Linearity Error: maximum deviation

between actual steps and the ideal one.

EL=Integral Linearity Error: maximum deviation

between any actual transition and the end point

correlation line.

4095

4094

4093

456

4093 4094 4095 4096

(1)

(2)

(3)

VDDA

VSSA

ai14395b

VREF+

4096

(or

depending on package)]

VDDA

4096

[1LSBIDEAL =

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