ST7LITEUS2 datasheet(38/136 Pages) STMICROELECTRONICS

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Supply, reset and clock management

ST7LITEUS2, ST7LITEUS5

38/136

This 16-bit register is read/write by software but can be written only once between two reset

events. It is cleared by hardware after a reset; When both MUXCR0 and MUXCR1 registers

are at 00h, the multiplexed PA3/RESET pin will act as RESET. To configure this pin as

output (Port A3), write 55h to MUXCR0 and AAh to MUXCR1.

These registers are one-time writable only.

●

To configure PA3 as general purpose output:

After power-on / reset, the application program has to configure the I/O port by writing

to these registers as described above. Once the pin is configured as an I/O output, it

cannot be changed back to a reset pin by the application code.

●

To configure PA3 as RESET:

An internally generated reset (such as POR, LVD, WDG, illegal opcode) will clear the

two registers and the pin will act again as a reset function. Otherwise, a power-down is

required to put the pin back in reset configuration.

Table 8.

Multiplexed IO register map and reset values

Address

(Hex.)

label

765432

0047h

MUXCR0

reset

value

MIR7

MIR6

MIR5

MIR4

MIR3

MIR2

MIR1

MIR0

0048h

MUXCR1

reset

value

MIR15

MIR14

MIR13

MIR12

MIR11

MIR10

MIR9

MIR8

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