| Os motores de busca de Datasheet de Componentes eletrônicos |
|
ST7DALIF2 Folha de dados(PDF) 132 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ST7DALIF2 Folha de dados(HTML) 132 Page - STMicroelectronics |
|
132 / 171 page ![]() Electrical characteristics ST7DALIF2 132/171 The RC oscillator and PLL characteristics are temperature-dependent and are grouped in four tables. Table 68. Operating voltage and startup time Symbol Parameter Min Typ Max Unit VDD(RC) Internal RC Oscillator operating voltage 2.4 5.5 V VDD(x4PLL) x4 PLL operating voltage 2.4 3.3 VDD(x8PLL) x8 PLL operating voltage 3.3 5.5 tSTARTUP PLL Startup time 60 PLL input clock (fPLL) cycles Table 69. RC oscillator and PLL characteristics (tested for TA = -40 to +85° C) @ VDD = 4.5 to 5.5 V Symbol Parameter Conditions Min Typ Max Unit fRC 1) Internal RC oscillator frequency (1) RCCR = FF (reset value), TA=25° C, VDD=5 V 760 kHz RCCR = RCCR0(2), TA=25° C, VDD=5 V 1000 ACCRC Accuracy of Internal RC oscillator with RCCR=RCCR0(2) TA=25° C, VDD=4.5 to 5.5 V -1 +1% TA=-40 to +85° C, VDD=5 V -5 +2 % TA=0 to +85° C, VDD=4.5 to 5.5 V -2(3) +2(3) % IDD(RC) RC oscillator current consumption TA=25° C, VDD=5 V 970(3) μA tsu(RC) RC oscillator setup time TA=25° C, VDD=5 V 10(2) μs fPLL x8 PLL input clock 1(3) MHz tLOCK PLL Lock time(4) 2ms tSTAB PLL Stabilization time(4) 4ms ACCPLL x8 PLL Accuracy fRC = 1 MHz@TA=25° C, VDD=4.5 to 5.5 V 0.1(5) % fRC = 1 MHz@TA=-40 to +85° C, VDD=5 V 0.1(5) % tw(JIT) PLL jitter period fRC = 1 MHz 125(6) µs JITPLL PLL jitter ( Δf CPU/fCPU)1 (6) % IDD(PLL) PLL current consumption TA=25° C 600(3) μA 1. If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device. 2. See Section 9.2: Internal RC oscillator adjustment on page 32 3. Data based on characterization results, not tested in production 4. After the LOCKED bit is set ACCPLL is max. 10% until tSTAB has elapsed. See Figure 11 on page 34. 5. Averaged over a 4ms period. After the LOCKED bit is set, a period of tSTAB is required to reach ACCPLL accuracy. 6. Guaranteed by design. |
|
Ligação URL |
| ALLDATASHEET é útil para você? [ DONATE ] |
Sobre Alldatasheet | Publicidade | Contato conosco | Privacy Policy | Link para a ficha técnica | roca de Link | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |