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ST7DALIF2 Folha de dados(PDF) 102 Page - STMicroelectronics

Nome de Peças ST7DALIF2
Descrição Electrónicos  Configurable watchdog timer
PDF  171 Pages
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Fabricante Electrônico  STMICROELECTRONICS [STMicroelectronics]
Página de início  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST7DALIF2 Folha de dados(HTML) 102 Page - STMicroelectronics

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Serial peripheral interface (SPI)
ST7DALIF2
102/171
Figure 46.
Single master/ single slave application
17.4.1
Slave select management
As an alternative to using the SS pin to control the Slave Select signal, the application can
choose to manage the Slave Select signal by software. This is configured by the SSM bit in
the SPICSR register (see Figure 48)
In software management, the external SS pin is free for other application uses and the
internal SS signal level is driven by writing to the SSI bit in the SPICSR register.
In Master mode:
SS internal must be held high continuously.
In Slave mode:
There are two cases depending on the data/clock timing relationship (see Figure 47):
If CPHA=1 (data latched on 2nd clock edge):
–SS internal must be held low during the entire transmission. This implies that in
single slave applications the SS pin either can be tied to VSS, or made free for
standard I/O by managing the SS function by software (SSM= 1 and SSI=0 in the
in the SPICSR register)
If CPHA=0 (data latched on 1st clock edge):
–SS internal must be held low during byte transmission and pulled high between
each byte to allow the slave to write to the shift register. If SS is not pulled high, a
Write Collision error will occur when the slave writes to the shift register (see Write
collision error (WCOL) on page 106).
Figure 47.
Generic SS timing diagram
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
8-BIT SHIFT REGISTER
MISO
MOSI
MOSI
MISO
SCK
SCK
SLAVE
MASTER
SS
SS
+5V
MSBit
LSBit
MSBit
LSBit
Not used if SS is managed
by software
MOSI/MISO
Master SS
Slave SS
(if CPHA=0)
Slave SS
(if CPHA=1)
Byte 1
Byte 2
Byte 3



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