SPC564A80L7 datasheet(8/157 Pages) STMICROELECTRONICS

Nome de Peças	SPC564A80L7

Descrição Electrónicos	Up to 4 multiply and accumulate operations per cycle

PDF	157 Pages

Scroll/Zoom	100%

Fabricante Electrônico	STMICROELECTRONICS [STMicroelectronics]

Página de início	http://www.st.com

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8 / 157 page

Introduction

SPC564A74L7, SPC564A80B4, SPC564A80L7

8/157

Doc ID 15399 Rev 9

Introduction

1.1

Document Overview

This document provides electrical specifications, pin assignments, and package diagrams

for the SPC564A80 series of microcontroller units (MCUs). For functional characteristics,

refer to the SPC564A80 Microcontroller Reference Manual.

1.2

Description

The microcontroller’s e200z4 host processor core is built on Power Architecture technology

and designed specifically for embedded applications. In addition to the Power Architecture

technology, this core supports instructions for digital signal processing (DSP).

The SPC564A80 has two levels of memory hierarchy consisting of 8 KB of instruction

cache, backed by 192 KB on-chip SRAM and 4 MB of internal flash memory. The

SPC564A80 includes an external bus interface, and also a calibration bus that is only

accessible when using the calibration tools.

This document describes the features of the SPC564A80 and highlights important electrical

and physical characteristics of the device.

SPC564A80L7 Folha de dados(PDF) 8 Page - STMicroelectronics