Application information

ST1S15

18/27

DocID023280 Rev 4

8.3

Layout guidelines

Due to the high switching frequency and peak current, the layout is an important design

step for all switching power supplies. If the layout is not fulfilled carefully, important

parameters such as: stability, efficiency, line and load regulation and output voltage ripple

may be compromised. Short, wide traces must be implemented for main current and for

power ground paths. The input capacitor must be placed as close as possible to the device

pin as well as the inductor and output capacitor. The feedback pin (FB) is a high

impedance node, so the interference can be minimized by placing the routing of the

feedback node as far as possible from the high current paths. A common ground node

minimizes ground noise.

Figure 22: Flip Chip layout recommended (not in scale)

MODE

GND

L

V

OUT

GIPG1401151337LM