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A6727 Folha de dados(PDF) 17 Page - STMicroelectronics |
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A6727 Folha de dados(HTML) 17 Page - STMicroelectronics |
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17 / 29 page ![]() DocID025003 Rev 1 17/29 A6727 Application details Figure 8. PWM control loop Compensation goal is to close the control loop assuring high DC regulation accuracy, good dynamic performances and stability. To achieve this, the overall loop needs high DC gain, high bandwidth and good phase margin. The loop bandwidth (F0dB) can be fixed choosing the right RF/RFB ratio, however, it should not exceed FSW / 2p. To achieve a good phase margin, the control loop gain has to cross 0 dB axis with -20 dB/decade slope. Figure 9 shows an asymptotic bode plot of a type III compensation. L R C OUT ESR R F C F C P R FB C S OSC V IN ∆V OSC + + _ _ V OUT V REF Z F Z FB PWM COMPARATOR ERROR AMPLIFIER R S AM16772v1 |
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