DocID029000 Rev 2

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HVLED001A

Pin settings

30

GD

9

Gate driver output. The output stage is able to drive the power MOSFET's and IGBT's gate.

VCC

10

Supply voltage of the IC.

Internal UVLO logic prevents the operation at voltages that are insufficient for the efficient gate

driving or signal processing. Both a bulk capacitor (typically around 10 µF) and a high frequency

filter capacitor (100 nF ceramic, mounted as close as possible to the device) are connected between

this pin and GND. An internal clamp structure prevents accidental low energy spikes damaging the

device. An external clamping device should be used to avoid the voltage applied to the VCC pin to

overcome the AMR.

Table 2. Pin description (continued)

Symbol Pin

Description