A6984 datasheet(13/47 Pages) STMICROELECTRONICS

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A6984

Device description

4.1

Output voltage adjustment

No external resistor divider is required to regulate fixed 3.3 V output voltage, connecting FB

to the VCC pin and VBIAS to the regulated output voltage (see Figure 1 on page 1). An

external voltage divider otherwise implements the output voltage adjustability.

Figure 4. Internal voltage divider for 3.3 V output voltage

The error amplifier reference voltage is 0.9 V typical.

The output voltage is adjusted accordingly with the following formula (see Figure 6):

Equation 1

4.1.1

Maximum output voltage

The constant on-time control scheme naturally requires a minimum cycle-by-cycle off time

to sense the feedback voltage and properly driving the switching activity.

The A6984 minimum off time, as reported in Table 2 on page 5, is 300 nsec typical and

400 nsec max.

The control loop generates the proper PWM signal to regulate the programmed output

voltage over the application conditions. Since the power losses are proportional to the

delivered output power, the duty cycle increases with the load current request.

The fixed minimum off time limits the maximum duty cycle, so the maximum output voltage,

depending on the selected switching frequency (see Section 4.2).

Figure 5 shows the worst case scenario for maximum output voltage limitation over the input

voltage range, that happens at the maximum current request and considering the upper

datasheet limit time for the minimum off time parameter.

A6984

OUT

0.9

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