LSM303D datasheet(45/52 Pages) STMICROELECTRONICS

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LSM303D

8.35

IG_SRC2 (35h)

This register contains the status for the inertial interrupt generator 2.

Reading at this address clears the IG_SRC2 (35h) IA bit (and the interrupt signal on the

corresponding interrupt pin) and allows the refresh of data in the IG_SRC2 (35h) register if

the latched option was chosen.

8.36

IG_THS2 (36h)

8.37

IG_DUR2 (37h)

Table 74. IG_SRC2 register

YHYL

XHXL

Table 75. IG_SRC2 register description

Interrupt generator 2 status. Default value: 0

(0: no interrupt has been generated; 1: one or more interrupts have been generated)

Z high. Default value: 0

(0: no interrupt; 1: Z high event has occurred)

Z low. Default value: 0

(0: no interrupt; 1: Z low event has occurred)

Y high. Default value: 0

(0: no interrupt; 1: Y high event has occurred)

Y low. Default value: 0

(0: no interrupt; 1: Y low event has occurred)

X high. Default value: 0

(0: no interrupt; 1: X high event has occurred)

X low. Default value: 0

(0: no interrupt; 1: X low event has occurred)

Table 76. IG2_THS2 register

THS6

THS5

THS4

THS3

THS2

THS1

THS0

Table 77. IG2_THS2 register description

THS[6:0]

Interrupt generator 2 threshold. Default value: 000 0000

Table 78. IG_DUR2 register

D6D5D4D3D2D1D0

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